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“úŽžF 2005”N4ŒŽ26“ú(‰Î) 14:30`15:30
êŠF “Œ–k‘åŠw‘åŠw‰@HŠwŒ¤‹†‰È —t‹L”O‰ïŠÙ 4ŠK‘匤CŽº
uŽtF Dr. Osamu Takahashi
Senior Technical Staff Member
SPC Circuit/Integration, Technical Team Manager
STI Design Center, Austin, TX
‰‰‘èF Introduction to a CELL processor and its Synergistic Processor Element
ŠT—vF
CELL is an extension of POWER architecture and is a multi-core
microprocessor, developed in a 90nm SOI technology. CELL contains 64b
POWER processor and 8 Synergistic Processor Elements (SPE), a 4-way SIMD
Processor. In SPE, CMOS static gates implement the majority of the logic.
Dynamic circuits are used in critical areas, occupying 19% of the
non-SRAM area. ISA, microarchitecture, and physical implementation are
tightly coupled to achieve a compact and power efficient design of SPE.
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FAX”Ô†: 022-795-7013
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